1. Field of the Invention
The present invention relates to a shift register circuit, and more particularly, to a shift register circuit capable of cyclically using flip-flops for saving the number of flip-flops that need to be used.
2. Description of the Prior Art
In digital circuits, a shift register, which generally includes a plurality of series connected flip-flops, is a widely used logic circuit unit, and can perform operations such as data registering, delay or conversion of serial and parallel output for input binary data. For example, when applied in liquid crystal display (LCD) driver circuits, the shift registers are utilized for sequentially providing pulse signals to a plurality of data output terminals according to a clock signal, such that data driving signals or gate driving signals can be outputted line-by-line for driving corresponding pixels.
Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are functional block diagrams of a source driver circuit 10 and a gate driver circuit 20 of a conventional LCD, respectively. The source driver circuit 10 includes a shift register 110, a sampling control circuit 120 and an output buffer 130. The gate driver circuit 20 includes a shift register 210 and an output buffer 230. In the source driver circuit 10, the shift register 110 is utilized for sequentially outputting pulse signals L1˜Ln to the sampling control circuit 120 for enabling latch circuits inside the sampling control circuit 120 (not shown in FIG. 1) according to an input pulse signal DIN1 and a clock signal CLK, so that video data RGB_Data can be sampled accordingly. Then, the output buffer 130 can output the data driving signals to data lines D1˜Dn according to sampled voltages of the video data RGB_Data. Similarly, in the gate driver circuit 20, the shift register 210 is utilized for sequentially providing pulse signals to the output buffer 230 for outputting the gate driving signals to scan lines S1˜Sn according to an input pulse signal DIN2 and a clock signal CLK2. Detailed operations of the LCD driver circuits are well known by those skilled in the art, and thus not described herein.
Please refer to FIG. 3. FIG. 3 is a schematic diagram of a conventional shift register 30. The shift register 30 can be the shift register 110 in FIG. 1 or the shift register 210 in FIG. 2, and includes series-coupled flip-flops FF1˜FFn and data output terminals OP1˜OPn. Each of the flip-flops FF1˜FFn further includes an input terminal D, an output terminal Q and a clock input terminal C, and is utilized for shifting a logic level received by the input terminal D to the output terminal Q according to a clock signal CLK received by the clock input terminal C. In general, the output terminal of each flip-flop is coupled to the input terminal of a next stage flip-flop and a corresponding data output terminal. Thus, when an input signal DIN is inputted to the input terminal of the first flip-flop FF1, the shift register circuit 30 then forward transfers a logic level of the input signal DIN stage-by-stage according to the clock signal CLK to output pulse signals to the data output terminals OP1˜Opn in order. As for the related signal sequence, please refer to FIG. 4.
Please further refer to FIG. 5. FIG. 5 is a schematic diagram of another conventional shift register 40. In the shift register 40, the input terminal of each flip-flop is further coupled to an input switch unit SW. The input switch unit SW includes a first switch SW1 and a second switch SW2, and is utilized for controlling the first switch SW1 and the second switch SW2 to couple the input terminal of each flip-flop to an output terminal of a former stage flip-flop or that of a next stage flip-flop according to a direction control signal UD, so as to enhance flexibility when using the shift register 40. For example, the input switch unit SW can short the first switch SW1 for coupling the input terminal of each flip-flop to the output terminal of a former stage flip-flop according to a low logic level of the direction control signal UD; and can short the second switch SW2 for coupling the input terminal of each flip-flop to the output terminal of a next stage flip-flop according to a high logic level of the direction control signal UD. In this case, when the input terminal of each flip-flop is coupled to the output terminal of a next stage flip-flop, the shift register 40 can then backward transfer the input signal UIN received by the input terminal of each flip-flop stage-by-stage according to the clock signal CLK, for outputting pulse signals to corresponding data output terminals OP1˜OPn in reverse order. As for the related signal sequence, please refer to FIG. 6.
Therefore, utilizing the input switch unit SW, the shift register 40 can switch the first switch SW1 and the second switch SW2 for forward or backward transferring the input signal according to the direction control signal UD, so as to output the pulse signals to the data output terminals OP1˜OPn in order or in reverse order. However, no matter how the input signal is transferred, each data output terminal needs one flip-flop for generating the pulse signal, and thus the number of the flip-flops has to be equal to that of the data output terminals. In some applications such as the gate driver circuits or the source driver circuits of the LCD, the shift register has to be used for transferring signals and sequentially outputting the signals to hundreds of data output terminals in order. In this case, hundreds of flip-flops are needed to realize the shift register. In fact, when the input signal is transferred in the shift register, only one or a few flip-flops are in operation (i.e. generating pulse signals) at the same time, but the remaining flip-flops are on standby. Thus, such shift registers waste circuit area and production cost.